1. Field of the Invention
The present invention relates to a method of fabricating a dual gate oxide of a semiconductor device. More particularly, the present invention relates to a method of forming a resultant gate oxide layer having a varying thickness on a single chip for fabricating a metal oxide semiconductor (MOS) device having different operating voltages.
2. Description of the Related Art
In general, an area of a chip where a thinner gate oxide is formed is used for a peripheral logic circuit requiring a high driving power, and an area of the same chip where a thicker gate oxide is formed is used for a memory cell circuit requiring a high breakdown voltage characteristic.
In order to implement MOS devices driven by different operating voltages in a single chip, rather complex photolithographic etching processes are required. For example, a step of forming gate oxide layers having different thicknesses and a step of selectively implanting impurities for the control of the respective threshold voltages are required.
Thus, as compared to a MOS device driven by a single operating voltage and having a single thickness, photolithographic etching processes are additionally required and masks used therein are necessarily fabricated.
FIGS. 1 through 7 illustrate cross-sectional views of sequential stages in a conventional method of fabricating a dual gate oxide.
A semiconductor substrate 10 for forming a dual gate oxide includes PMOS forming regions 13 and 14 and NMOS forming regions 11 and 12.
The NMOS forming regions 11 and 12 include a first forming region 11, where a thick gate oxide is to be formed, and a second NMOS forming region 12, where a thin gate oxide is to be formed. The PMOS forming regions 13 and 14 include a first PMOS forming region 13, where a thick gate oxide is to be formed, and a second PMOS forming region 14, where a thin gate oxide is to be formed.
Referring to FIG. 1, the conventional method of fabricating the dual gate oxide includes forming a first photoresist (PR) pattern P1 on the substrate 10 to cover the NMOS forming regions 11 and 12, forming N wells in the PMOS forming regions 13 and 14 using the first PR pattern P1 as a mask, and ion implanting an impurity 20 for controlling the threshold voltages into the N wells. After implanting the impurity 20, the first PR pattern P1 is removed.
Referring to FIG. 2, a second PR pattern P2 is formed on the substrate 10 to cover the PMOS forming regions 13 and 14. Then, P wells are formed in the NMOS forming regions 11 and 12 using the second PR pattern P2 as a mask. Next, an impurity 30 for controlling the threshold voltages is ion implanted into the P wells. After implanting the impurity 30, the second PR pattern P2 is removed.
Referring to FIG. 3, in order to implant an impurity 40 for controlling a threshold voltage into the first PMOS forming region 13, a third PR pattern P3 is formed on the substrate 10 for use as a mask during the impurity implantation. After the implantation of the impurity 40, the third PR pattern P3 is removed.
Referring to FIG. 4, in order to implant an impurity 50 for controlling a threshold voltage into the first NMOS forming region 11, a fourth PR pattern P4 is formed on the substrate 10 for use as a mask during the impurity implantation. After the implantation of the impurity 50, the fourth PR pattern P4 is removed.
Referring to FIG. 5, a first gate oxide 60 is formed over an entire surface of the substrate 10.
Referring to FIG. 6, a fifth PR pattern P5 is formed on the first gate oxide 60 over the second NMOS forming region 12 and the second PMOS forming region 14. The first gate oxide 60 over the first NMOS forming region 11 and the first PMOS forming region 13 is then etched using the fifth PR pattern P5 as a mask for removal.
Referring to FIG. 7, a second gate oxide 70 is formed on the substrate 10 and the first gate oxide 60 to cover the NMOS and PMOS forming regions 11, 12, 13, and 14. Resultantly, a dual gate oxide having both a thick gate oxide layer and a thin gate oxide layer is formed in a single chip.
As described above, the conventional process for fabricating the dual gate oxide involves various photolithographic etching steps, thereby making the process complex and costly.